Journal
publications, Submitted to Journals, Book sections, Conferences, theses
1.
G. Cyr,
G. Bois, and E. M. Aboulhamid, "Generation of processor interface for SoC using VSIA recommendations," IEE Proceedings
- Computers and Digital Techniques, vol. 151, no. 05, pp. 367-376, Sep.
2004. 2.
W. N.
N. Hung, X. Song, E. M. Aboulhamid, A. Kennings, and A. Coppola,
"Segmented channel routability via satisfiability," ACM Transactions on Design
Automation of Electronic Systems (TODAES), vol. 9, no. 4, pp. 517 - 528,
October 2004. 3.
M. Azizi, X. Song, and E. M. Aboulhamid, "A Case Study
on the Verification of Cache Coherence Protocols," International
Journal of Computers and Applications, ACTA Press, vol. 26, no. 1, pp.
38-47, Jan. 2004. 4.
N. Chabini, I. Chabini, E. M.
Aboulhamid, and Y. Savaria, "Methods for Minimizing Dynamic Power Consumption
in Synchronous Designs with Multiple Supply Voltages," IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
vol. 22, no. 3, pp. 346 -351, March 2003. 5.
N. Chabini, E. M. Aboulhamid, 6.
W. N.
N. Hung, X. Song, and E. M. Aboulhamid, "BDD Minimization by Scatter
Search," IEEE Transactions on CAD, vol. 21, no. 8, pp. 974-979,
August 2002. 7.
Y.
Wang, X. Song, M. Aboulhamid, and H. Shen,
"Adder Based Residue to Binary Number Converters for (2n-1,2n,2n+1)," IEEE
Transactions on Signal Processing, vol. 50, no. 7, pp. 1772 -1779, Jul.
2002. PDF 8. C. Bourhfir, E.
Aboulhamid, R. Dssouli, and N. Rico, "A test
case generation approach for conformance testing of SDL systems," Computer
Communications, vol. 24, pp. 319-333, March/April 2001. PDF 9. F.-R. Boyer, E. M. Aboulhamid, Y. Savaria,
and M. Boyer, "Optimal Design of Synchronous Circuits Using Software
Pipelining Techniques," ACM Transactions on Design Automation of
Electronic Systems (TODAES), vol. 6, pp. 516-532, Oct. 2001. PDF 10. R. Dssouli, K. Saleh, E. M. Aboulhamid, A. En-Nouaary,
and C. Bourhfir, "Test development for
communicating protocols: towards automation," Computer Networks,
vol. 31, pp. 1835-1872, June 1999. 11. E. Bennour and
E. M. Aboulhamid, "Lower-bounds on the Iteration and Initiation Interval
of Functional Pipelining and Loop Folding," Design Automation for
Embedded Systems, Kluwer, vol. 1, pp. 333-355,
October 1996. PDF 12. Y. Karkouri, E.
M. Aboulhamid, E. Cerny, and A. Verreault,
"Use of Fault Dropping for Multiple Fault Analysis," IEEE
Transactions on Computers, vol. 43, pp. 98-103, Jan 1994. PDF 13. E. M. Aboulhamid, Y. Karkouri,
and 14. M. Meknassi, E.
M. Aboulhamid, and E. Cerny, "Comment on
"Algorithm for the graph-partitioning problem using a problem
transformation method"," Computer-Aided Design, vol. 24, pp.
397-398, July 1992. 15. Y. Karkouri and E. M. Aboulhamid,
"Complexité du test des circuits logiques," Technique et Science
Informatiques, vol. 9, pp. 273-287, Septembre 1990. 16. E. M. Aboulhamid, E. Cerny,
M. Loughzail, and M. Côté
"Testing and the VHDL Environment," Test & Measurement World,
vol. 9, pp. 77-84, April 1989. 17. E. Cerny, E. M. Aboulhamid,
G. Bois, and J. Cloutier, "Built-In Self Test
of a CMOS ALU," IEEE Design&Test of
Computers, vol. 5, pp. 38-48, Aug. 1988. 18. E. M. Aboulhamid and 19. E. M. Aboulhamid and E. Cerny, "A Class of Test Generators for Built-In
Testing," IEEE Transactions on Computers, vol. C-32, pp. 957-959,
Oct. 1983. |
20. J. Lapalme, E. M. Aboulhamid, and G.
Nicolescu, "A New Efficient EDA Tools Design Methodology," ACM
Transactions on Embedded Computing Systems, 16 pages, submitted February
2005. |
21. G. Bois, L. Filion, A. Tsikhanovich,
and E. M. Aboulhamid, "Modélisation,
raffinement et techniques de programmation orientée objet avec SystemC," in La spécification et la validation des
systèmes hétérogènes embarqués, A. A. Jerraya and G.
Nicolescu, Eds.: Hermes,
2004, pp. 171-207. 22. L. Charest, E.-M. Aboulhamid, and G. Bois,
"Applying patterns and multi-paradigm approaches to hardware/software
design and reuse," in Patterns And Skeletons For
Parallel And Distributed Computing, F. Rabhi
and S. Gorlatch, Eds. London: Springer-Verlag, 2002, pp. 30. 23. E. M. Aboulhamid, M. Azizi,
and X. Song, "Hardware Design and Verification Methods," in Encyclopedia
of Computer Science and Technology, vol. 42, supplement 27, A. Kent and
J. G. Williams, Eds., 2000, pp. 67-91. 24. E. M. Aboulhamid and |
25. A. T. Abdel-Hamid, S. Tahar, and E. M.
Aboulhamid, "A Public-Key Watermarking Technique for IP Designs," Proc.
Design, Automation and Test in Europe Conference and Exhibition, Munich,
Germany, 7-11 March, 2005, pp. 330-335. 26. A. Chureau, Y. Savaria, and E. M.
Aboulhamid, "The Role of Model-Level Transactors
and UML in Functional Prototyping of Systems-on-Chip: a Software-radio
Application," Proc. Design, Automation and Test in Europe Conference
and Exhibition, Munich, Germany, 7-11 March, 2005, pp. 698-703. 27. N. Gorse, M. Metzger, J. Lapalme, E. M.
Aboulhamid, Y. Savaria, and G. Nicolescu, "Enhancing ESys.Net with a
Semi-Formal Verification Layer," Proc. 16th IEEE International
Conference on Microelectronics (ICM'04), 28. N. Gorse, P. Bélanger,
E. M. Aboulhamid, and Y. Savaria, "Mixing Linguistic and Formal
Techniques for High-Level Requirements Engineering," Proc. 16th IEEE
International Conference on Microelectronics (ICM'04), Tunis, Tunisia,
Dec., 2004, pp. 339-342. 29. M. T. Zerarka,
J. P. David, and E. M. Aboulhamid, "High speed emulation of gene
regulatory networks using FPGAs," Proc.
47th Midwest Symposium onCircuits and Systems
(MWSCAS '04), 30. D. L. Truong, O. Cherkaoui,
H. Elbiaze, N. Rico, and M. Aboulhamid, "A
policy-based approach for user controlled lightpath
provisioning," Proc. IEEE/IFIP Network Operations and Management
Symposium (NOMS), 2004, pp. 859-872 Vol.1. 31. N. Gorse, E. M. Aboulhamid, and Y.
Savaria, "Consistency validation of high-level requirements," Proc.
4th IEEE International Workshop on System-on-Chip for Real-Time Applications,
Banff, Canada, 19-21 July, 2004, pp. 93-98. 32. L. Charest, E. M. Aboulhamid, and G. Bois,
"Using design patterns for type unification and introspection in SystemC," Proc. 4th IEEE International Workshop
on System-on-Chip for Real-Time Applications, Banff, Canada, 19-21 July,
2004, pp. 45-50. 33. A. Chureau, Y. Savaria, and E. M.
Aboulhamid, "Interface-based design of systems-on-chip using
UML-RT," Proc. 4th IEEE International Workshop on System-on-Chip for
Real-Time Applications, 2004, pp. 39-44. 34. [J. Lapalme, E. M. Aboulhamid, G.
Nicolescu, L. Charest, J.-P. David, F. Boyer, and G. Bois, "ESys.NET: A
New Solution for Embedded Systems Modeling and Simulation," Proc. ACM
SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for
Embedded Systems (LCTES'04), Washington, DC, June 11-13, 2004, pp.
107-114. 35. D. Quinn, B. Lavigueur,
G. Bois, and E. M. Aboulhamid, "A System Level Exploration Platform and
Methodology for Network Applications Based on Configurable Processors," Proc.
Design Automation and Test in Europe Conference & Exhibition, Paris,
France, Feb., 2004, pp. 364 - 369. 36. O. Benny, M. Rondonneau,
J. Chevalier, G. Bois, E. M. Aboulhamid, and F.-R. Boyer, "SoC Software Refinement Approach for a SystemC Platform," Proc. DVCon
2004, Design & Verification Conference & Exhibition, San Jose,
CA, March, 2004, pp. 7 pages. 37. J. Lapalme, E. M. Aboulhamid, G.
Nicolescu, L. Charest, J.-P. David, F. Boyer, and G. Bois, "Net
Framework - A Solution for the Next Generation Tools for System-Level
Design?" Proc. Design Automation and Test in Europe Conference &
Exhibition, 38. L. Sun, E. M. Aboulhamid, and J. P. David,
"Network on Chip using a Reconfigurable Platform," Proc. 46 IEEE
Midwest Symposium on Circuits and Systems, Cairo, Egypt, Dec., 2003, pp.
4 pages. 39. F. Boyer, Y. Liping,
E. M. Aboulhamid, L. Charest, and G. Nicolescu, "Multiple Simplescalar Processors with Introspection under SystemC," Proc. 46 IEEE Midwest Symposium on
Circuits and Systems, Cairo, Egypt, Dec., 2003, pp. 5 pages. 40. E. M. Aboulhamid and J. Lapalme,
"Recent Trends in Hardware/Software Description Languages," Proc.
The 15th International Conference on Microelectronics, ICM 2003, Cairo,
Egypt, Dec., 2003, pp. 185-188. 41. A. Tsikhanovich,
E. M. Aboulhamid, and G. Bois, "Object-Oriented Techniques in Hardware
Modeling using SystemC," Proc. First Annual
Northeast Workshop on Circuits and Systems, 42. J. Chevalier, O. Benny, M. Rondonneau, G. Bois, E.-M. Aboulhamid, and J.-F. Boyer,
"SPACE: A Hardware/Software SystemC modeling
platform including an RTOS," Proc. Forum on Design Languages (FDL03),
43. S. Regimbal,
J.-F. Lemire, Y. Savaria, G. Bois, E. M.
Aboulhamid, and A. Baron, "Automating Functional Coverage Analysis Based
On An Executable Specification," Proc. The 3rd IEEE International
Workshop on System-on-Chip for Real-Time Applications, Calgary, Canada,
June 30 - July 2, 2003, pp. 228-234. 44. J.-F. Lemire, S.
Regimbal, G. Bois, Y. Savaria, E. M. Aboulhamid,
and A. Baron, "Implementing e Assertion Checkers from an SDL Executable
Specification," Proc. DVCon 2003, Design
& Verification Conference & Exhibition, San Jose, CA, 2003. 45. A. Abdel-Hamid, S. Tahar, and E. M.
Aboulhamid, "IP Watermarking Techniques: Survey and Comparison," Proc.
2003 International Workshop on System-on-Chip for Real-Time Applications,
46. N. Chabini, Isamel Chabini, E. M.
Aboulhamid, and Y. Savaria, "Unification of Basic Retiming and Supply
Voltage Scaling to Minimize Dynamic Power Consumption for Synchronous Digital
Designs," Proc. GLSVLSI 2003, Washington D.C., April 28-29, 2003,
pp. 221-224. 47. L. Charest and E. M. Aboulhamid, "A
VHDL/SystemC Comparison in Handling Design
Reuse," Proceedings of 2002 International Workshop on System-on-Chip
for Real-Time Applications, Banff, Canada, July 6-7, 2002, pp. 11 48. L. Charest, E. M. Aboulhamid, C.
Pilkington, and P. Paulin, "SystemC
Performance Evaluation Using A Pipelined DLX Multiprocessor," Proceedings
of Design and Test in Europe Designers' Forum, 49. L. Charest, E. M. Aboulhamid, and A. Tsikhanovich, "Designing with SystemC:
Multi-Paradigm Modeling and Simulation Performance Evaluation," Proceedings
of The 11th Annual International HDL Conference, San Jose, CA, March 11-12,
2002, pp. 33-45. PDF 50. L. Filion, G. Bois, and E. M. Aboulhamid,
"Syslib: A System-Level Language Extended from
Cynlib for SoC," Proceedings
of The 11th Annual International HDL Conference, San Jose, CA, March 11-12,
2002, pp. 191-197. 51. S. Regimbal,
J.-F. Lemire, Y. Savaria, G. Bois, and E. M.
Aboulhamid, "Applying Aspect-Oriented Programming to Hardware
Verification with e," Proceedings of The 11th Annual International HDL
Conference, San Jose, CA, March 11-12, 2002, pp. 68-75. 52. E. M. Aboulhamid, "New
Hardware/Software Design Methodologies," Proceedings of The 13th
International Conference on Microelectronics (invited talk), Rabat, Morocco,
Oct. 29-31, 2001, pp. 3-5. 53. F. R. Boyer, E. M. Aboulhamid, and Y.
Savaria, "Minimizing Sensitivity to Clock Skew Variations Using Level
Sensitive Latches," Proceedings of ECCTD'01: European Conference on
Circuit Theory and Design, Espoo, Finland, August
28-31, 2001, pp. 253-256. PDF 54. N. Chabini, E.
M. Aboulhamid, and Y. Savaria, "Reducing Register and Phase Requirements
for Synchronous Circuits Derived Using Software Pipelining Techniques,"
Proceedings of IEEE Computer Society Workshop on VLSI, 55. N. Chabini, E.
M. Aboulhamid, and Y. Savaria, "Minimizing Register Requirements for
Synchronous Circuits Derived using Software Pipelining Techniques,"
Proceedings of The 13th International Conference on Microelectronics, Rabat,
Morocco, Oct. 29-31, 2001, pp. 249-252.
PDF 56. N. Chabini, E.
M. Aboulhamid, and Y. Savaria, "Determining Schedules for Reducing Power
Consumption Using Multiple Supply Voltages," Proceedings of The
International Conference on Computer Design (ICCD'2001), 57. N. Chabini,
E.-M. Aboulhamid, and Y. Savaria, "Efficient Methods for Reducing
Register and Phase Requirements for Synchronous Circuits Derived Using
Software Pipelining Techniques," Proceedings of 15th European Conference
on Circuit Theory and Design (ECCTD'2001), Espoo,
Finland, August 28 - 31, 2001. PDF 58. L. Charest, M. Reid, E. M. Aboulhamid, and
G. Bois, "A Methodology for Interfacing Open Source SystemC
with a Third Party Software," Proceedings of Design Automation and Test
in Europe Conference & Exhibition, Munich, Germany, 13-16 March, 2001,
pp. 16-20. PDF 59. G. Cyr, G. Bois, and M. Aboulhamid,
"Synthesis Of Communication Interface For Soc Using VSIA
Recommendations," Proceedings of DATE Design Forum, Munich, Germany,
13-16 March, 2001, pp. 155-159. 60. Y. Héneault, G.
Bois, and E. M. Aboulhamid, "A Fast Hardware Co-Specification and
Co-Simulation Methodology Integrated in a H/S Co-Design Platform,"
Proceedings of The 13th International Conference on Microelectronics, 61. M. Reid, L. Charest, A. Tsikhanovich, E. M. Aboulhamid, and G. Bois,
"Implementing a Graphical User Interface for SystemC,"
Proceedings of The 10th International HDL Conference (HDLCon),
Santa Clara, CA, Feb. 28 - March 1, 2001, pp. 224-231. 62. M. Azizi, E.
Aboulhamid, and S. Tahar, "Sequential and Distributed Simulations Using
Java Threads," Proceedings of Parelec, 63. F.-R. Boyer, E. M. Aboulhamid, and Y.
Savaria, "An Efficient Verification Method for a Class of Multi-phase
Sequential Circuits," Proceedings of IEEE International Conference on
Electronics, Circuits and Systems, 64. M. Azizi, E. M.
Aboulhamid, and S. Tahar, "Properties Coverification
for HW/SW Systems," Proceedings of 2nd Electronic Circuits and Systems
Conference (ECS'99), 65. M. Azizi, E.-M.
Aboulhamid, and S. Tahar, "Multithreading-Based Coverification
Technique of HW/SW Systems," Proceedings of International Conference on
Parallel and Distributed Processing Techniques and Applications (PDPTA'99),
Las Vegas (Nevada), June, 1999, pp. 1999-2005. 66. C. Bourhfir, R. Dssouli, E. M. Aboulhamid, and N. Rico, "A test case
generation tool for conformance testing of SDL systems," Proceedings of
SDL'99, Montreal, Qc., Canada, June, 1999, pp. 405-419. 67. A. El-Aboudi and
E.-M. Aboulhamid, "A New Algorithm for the Verification of Timing
Diagrams Realizability," Proceedings of
ISCAS'99, Orlando,Florida, USA, May 30 - June 2,
1999, pp. 314-317. PDF 68. Y. Henneault, G.
Bois, E. M. Aboulhamid, J. Baillairgé, and P. Yousefpour, "Renoir Extensions to Support a H/S
Co-Design Methodology Based on the VSIA Recommendations," Proceedings of
16th Annual Intern. Conf. Mentor Graphics User's Group, 69. Y. Henneault, G.
Bois, E. M. Aboulhamid, J. Baillargé, and P. Yousefpour, "Picasso : A H/S Capture Tool Based on
VSIA Recommendations," Proceedings of International Workshop on IP-Based
Synthesis and System Design, 70. Y. Wang, X. Song, and M. Aboulhamid,
"A new algorithm for RNS magnitude comparison based on New Chinese
Remainder Theorem II," Proceedings of Proceedings. Ninth 71. M. Azizi, E. M.
Aboulhamid, and S. Tahar, "Multi-Threading Based Coverificatin
of Embedded Systems," Proceedings of Workshop on Issues in Block-Based
System Design (IPBlock'98), 72. M. Azizi, E.-M.
Aboulhamid, and I. E. Bennour, "Covérification des systèmes intégrés," Proceedings of TISVA'98, Oujda , Morocco, April, 1998, pp. 234-240. 73. C. Bourhfir, R. Dssouli, E. Aboulhamid, and N. Rico, "A guided
incremental test case generation procedure for conformance testing for CEFSM
specified protocols," Proceedings of The IFIP 11th International
Workshop on Testing of Communicating Systems (IWTCS'98), Tomsk
(Russia), Aug 31- Sept 2, 1998, pp. 279-294. PDF 74. F. R. Boyer, E. M. Aboulhamid, Y. Savaria,
and I. E. Bennour, "Optimal design of
synchronous circuits using software pipelining techniques," Proceedings
of IEEE/ACM International Workshop on Logic Synthesis, Granlibakken
Resort, Lake Tahoe, California, June 7-10, 1998. 75. F. R. Boyer, E. M. Aboulhamid, Y. Savaria,
and I. E. Bennour, "Optimal design of
synchronous circuits using software pipelining techniques," Proceedings
of International Conference on Computer Design, Austin, Texas, USA, October
5-7, 1998, pp. 62-67. 76. N. Chabini, E.
M. Aboulhamid, Y. Savaria, and I. E. Bennour,
"A Static Method for System Performance Estimation," Proceedings of
The Tenth International Conference on Microelectronics, Monastir,
Tunisia, December 14-16, 1998, pp. 111-114. 77. A. El-Aboudi, E.
M. Aboulhamid, and E. Cerny, "Realizability and synthesis of interface
controllers," Proceedings of 6th International Workshop on
Hardware/Software Co-Design (Codes/CASHE '98), Seattle, Washington, March
15-18, 1998. 78. A. El-Aboudi, E.
M. Aboulhamid, and E. Cerny, "Synthesis of
Interface Controllers for Timing Diagram Specifications," Proceedings of
Custom Integrated Circuits Conference (CICC 98), Santa Clara, CA, May 11-14,
1998, pp. 89-92. PDF 79. A. El-Aboudi, E.
M. Aboulhamid, and E. Cerny, "Verification of
Synchronous Realizability of Interfaces from Timing
Diagram Specifications," Proceedings of International Conference on
Microelectronics (ICM'98), 80. A. El-Aboudi, E.
M. Aboulhamid, and E. Cerny, "Interface Block
Synthesis under Real-Time Constraints," Proceedings of Workshop on
Issues in Block-Based System Design (IPBlock'98), 81. Y. Wang, X. Song, and M. Aboulhamid,
"Residue to Binary Number Converters for (2n-1, 2n, 2n+1),"
Proceedings of 8TH Great Lakes Symposium on VLSI, 82. C. Bourhfir, R. Dssouli, E. M. Aboulhamid, and N. Rico, "Automatic
executable test case generation for extended finite state machine
protocols," Proceedings of IFIP WG 6.1 10th International Workshop on
Testing of Communicating Systems (IWTCS'97), Cheju
Island, Korea, September 8-10, 1997, pp. 75-90. PDF 83. E. Cerny, Y.
Wang, and E. M. Aboulhamid, "Scheduling and Interface Controller
Synthesis under Real-Time Constraints," Proceedings of Journées Bordelaises Ordres partiels et algorithmes distribués, June 5-6, 1997, pp. 25. 84. E. Cerny, Y.
Wang, and M. Aboulhamid, "Discrete-Time Scheduling under Real-Time
Constraints," Proceedings of IFIP International Workshop on Logic and
Architecture Synthesis (IWLAS'97), Grenoble,
France, December 16-18, 1997, pp. 195-204. PDF 85. I. E. Bennour
and E. M. Aboulhamid, "Register allocation using circular FIFOs," Proceedings of 1996 IEEE International
Symposium on Circuits and Systems, 86. I. E. Bennour,
M. Langevin, and E. M. Aboulhamid,
"Performance Analysis for Hardware/Software Cosynthesis,"
Proceedings of Canadian Conference on Electrical and Computer Engineering, 87. I. Bennour and
E. M. Aboulhamid, "Maximal Performance of Pipelined Circuits Under
Hardware Constraints," Proceedings of Canadian Conference on Electrical
and Computer Engineering, 88. I. E. Bennour
and E. M. Aboulhamid, "A register allocation problem solved by
constraint logic programming and interval arithmetic," Proceedings of 95
International Logic Programming Symposium, Workshop on Interval Constraints, 89. E. M. Aboulhamid and P. Yousefpour, "Comparing SDL vs. VHDL for H/W
Modeling," Proceedings of Fifth BNR/NT Design Forum, Ottawa, Ont., Dec.
6-8, 1994, pp. 11.1-11.6. 90. E. M. Aboulhamid, "VHDL as a Teaching
Tool," Proceedings of Fourth Canadian Conference on Computer Engineering
Education, 91. M. Bourahla, K.
M. Soh, E. M. Aboulhamid, and S. Curry,
"Modeling techniques with VHDL for jitter performance analysis,"
Proceedings of VHDL International Users Forum Conference, 92. Y. Karkouri, E.
M. Aboulhamid, and E. Cerny, "Test Pattern
Generation for Multiple Stuck-at Faults," Proceedings of European Test
Conference ETC'93, 93. M. Meknassi and
E. M. Aboulhamid, "High Quality Multi-Partitioning of Networks using
Alternating Objectives," Proceedings of Canadian Conference on VLSI, 94. Y. Karkouri and
E. M. Aboulhamid, "Multiple Fault Diagnosis in Logic Circuits,"
Proceedings of Canadian Conference on VLSI, 95. M. Meknassi, E.
M. Aboulhamid, and E. Cerny, "A partitioning
algorithm for large graphs," Proceedings of Canadian Conference on VLSI,
96. E. Cerny, E. M.
Aboulhamid, C. Mauras, and P. Rioux,
"Test Generation using Cross-Observability
Calculations," Proceedings of Euro ASIC 91, Paris, May 27-31, 1991. 97. A. Verreault, E.
M. Aboulhamid, and Y. Karkouri, "Multiple
Fault Analysis using a Fault Dropping Technique," Proceedings of The
21st Fault-Tolerant Computing Symposium, 98. E. M. Aboulhamid and M. E. Cordeau, "System Level Modeling in VHDL using Timed
Petri Nets," Proceedings of First European Conference on VHDL, IMT
Marseille France, 1990. 99. M. Bourahla, E. Cerny, and E. M. Aboulhamid, "VHDL Modeling of
Boundary-Scan Architecture," Proceedings of 20th Annual Modeling and
Simulation Conference, 100.
E. Cerny, E. M. Aboulhamid, and S. Curry, "Some
Elements for High-Level Modeling in VHDL," Proceedings of Canadian
Conference on VLSI, Vancouver, B.C., 1989, pp. 91-98. 101.
E. Cerny, E. M. Aboulhamid, and S. Curry, "Basic
Structures for High-Level VHDL Modeling," Proceedings of VHDL in the
Design Environment, Redondo Beach, CA, 1989. 102.
M. Eleuldj, E. M. Aboulhamid, and E. Cerny,
"Fault Diagnosis of Multistage Interconnection Networks,"
Proceedings of Reliability' 89 in Computer Science, Jasna
pod 103.
M. Eleuldj, E. M. Aboulhamid, and E. Cerny,
"Fault Diagnosis of Multistage Cube Interconnection Networks,"
Proceedings of Canadian Conference on VLSI, 104.
Y. Karkouri, E. M. Aboulhamid, E. Cerny,
and J. Rajski, "Improved Multiple Fault
Analysis in Digital MOS Networks," Proceedings of Canadian Conference on
VLSI, KARK 89, 1989, pp. 267-274. 105.
M. Eleuldj, E. M. Aboulhamid, and E. Cerny,
"A Class of Fault-Tolerant Cellular Permutation Networks,"
Proceedings of IEEE International Conference on Computer Design, 106.
E. M.
Aboulhamid and M. Eleuldj, "C-Testability of
One and Two-Dimensional Combinational Unidirectional Iterative Arrays under
Sequential Fault Model," Proceedings of 1987 Canadian Conference on
VLSI, 107.
E. M.
Aboulhamid, Y. Karkouri, 108.
E. M.
Aboulhamid, Y. Karkouri, 109.
E. M.
Aboulhamid, M. Loughzail, M. Côté,
and E. Cerny, "Evaluation of the VHDL
Environment Using Benchmark Results on a VAX-8600 and a Micro-VAX,"
Proceedings of 2nd VHDL Users Conference, 110.
E. Cerny, G. Bois, and E. M. Aboulhamid, "Built-In
Self-Test of a CMOS ALU," Proceedings of 1986 International Symposium on
Fault Tolerant Computing, FTCS-16, 111.
E. M.
Aboulhamid, "Efficient Testing & Truth Table Verification of
Unilateral Combinational Iterative Arrays," Proceedings of IEEE
International Conference On Computer-Aided Design, Santa Clara, CA, Nov.
18-21, 1985, pp. 68-70. 112.
E. M.
Aboulhamid and E. Cerny, "Concurrent Fault
Detection by Imperfect Duplication," Proceedings of IEEE International
Conference on Computer Aided Design, Santa Clara, CA, Sept., 1983, pp. 77-78. 113.
E. Cerny and E. M. Aboulhamid, "Built-In Testing of pI-testable Iterative Arrays," Proceedings of 1983
International Symposium on Fault Tolerant Computing, FTCS-13, Milano ( 114.
E. Cerny and E. M. Aboulhamid, "An Arithmetic/Logic
Unit with Built-in Testing," Proceedings of Fault Tolerant Systems &
Diagnostics VI, 115.
E. M.
Aboulhamid and E. Cerny, "A Class of Test
Generators for Built-In Testing," Proceedings of 1982 International
Conference on Circuits and Computers, ICCC-82, New York, 1982. |
116.
N. Chabini, Méthodes pour
améliorer la qualité des implantations matérielles de systèmes informatiques,
Ph.D., Dép. d'Informatique et de Recherche
Opérationnelle, Université de Montréal, Sep. 2001. PDF 117.
F.-R. Boyer, Optimisation lors de la synthèse de
circuits à partir de langages de haut niveau, Ph.D.,
Dép. d'Informatique et de Recherche Opérationnelle, Université de Montréal,
Juin 2001. PDF 118.
M. Azizi, Coverification
des Systèmes Integrés, Ph.D.,
Dép. d'Informatique et de Recherche Opérationnelle, Université de Montréal,
Juin 2001. PDF 119.
M. Reid, Visualisation interactive des résultats de
simulation de matériel modélisé avec SystemC, M.Sc., Dép. d'Informatique et de Recherche
Opérationnelle, Université de Montréal, Août 2001. 120.
C. Bourhfir, Génération
automatique de cas de test pour les systèmes modélisés par des machines à
états finis communicantes, Ph.D., Dép.
d'Informatique et de Recherche Opérationnelle, Université de Montréal, 1999. PDF 121.
N. Chabini, Estimation des
performances du système PULSE V1 pour des applications de nature itérative,
M.Sc., Dép. d'Informatique et de Recherche
Opérationnelle, Université de Montréal, 1998. 122.
I.-E. Bennour, Estimation
de la performance et méthodes d'allocation dans la synthèse de systèmes
numériques, Ph.D., Dép. d'Informatique et de
Recherche Opérationnelle, Université de Montréal, 1996. PDF
(ch. 1) 123.
M. Meknassi, Multi-partitionnment des réseaux pour des
applications en VLSI, Ph.D., Dép.
d'Informatique et de Recherche Opérationnelle, Université de Montréal, Déc.
1993. 124.
P. Girodias, De l'à propos du modèle de simulation
optimiste pour l'implantation de VHDL dans un environnement informatique
distribué, M.Sc., Dép. d'Informatique et de
Recherche Opérationnelle, Université de Montréal, 1992. 125.
Y. Karkouri, Analyse et
génération de vecteurs de tests pour les pannes multiples, Ph.D., Dép. d'Informatique et de Recherche
Opérationnelle, Université de Montréal, Sept. 1992. 126.
A. Verreault, Analyse des
pannes multiples utilisant une technique d'élimination rapide, M.Sc., Dép. d'Informatique et de Recherche
Opérationnelle, Université de Montréal, 1991. 127.
M. Bourahla, Modélisation
des circuits VLSI et conception en vue de leur testabilité, M.Sc., Dép. d'Informatique et R.O., Université de
Montréal, Juin 1989. 128.
M. Eleuldj, Testabilité et
tolérance aux fautes des circuits logiques à structure regulière,
Ph.D., Dép. d'Informatique et R.O., Université de
Montréal, Juin 1989. 129.
M. Loughzail, Performances
et caractéristiques d'un environnement du langage de description de matériel
VHDL, M.Sc., Dép. d'Informatique et R.O.,
Université de Montréal, 1988. 130.
Y. Karkouri, Une méthode
d'analyse des fautes dans les circuits VLSI, M.Sc.,
Dép. d'Informatique et de Recherche Opérationnelle, Université de Montréal,
1987. |
|
2005-03-16 |