For example, starting with your behavioral description of the functions you want to turn into silicon, you can explore the advantages and disadvantages of pipelineing (which is a part of rolling and unrolling loops as discussed briefly in Chapter 3) by merely changing the constraints on your schedule. No need to go back, change your source code, and take the time to analyze, elaborate, time, and schedule your design again.
The above illustration shows that by changing the initiation you can explore throughput and area considerations of pipelining loops. This powerful tool can help you achieve the optimum speed and size of your design. Briefly, pipelining is a way to increase throughput (latency) but at the expense of chip area and of Finite State Machine complexity. The Behavioral Synthesis class devotes a chapter to the topic of pipelining.
We have also not talked in this tutorial about implementing memories into our design. The Synopsys MemWrap tool is specifically designed to allow you to easily incorporate memories and graphically establish timing, control, and access. Briefly, MemWrap allows you to specify memories as arrays that you simply read from and write to. MemWrap enables you to explore different memory architectures and eliminates the need for you, the designer, to understand the DesignWare synthetic library format.
Above is the GUI of the MemWrap tool showing the timing area where you can point and click to set or change read/write timing. Ater this timing is established for a target memory, you read and write an array and MemWrap handles the rest for you.
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