You can also set these in your .cshrc file. For example:
setenv ARCH sparcOS5
setenv SYNOPSYS /u/release/2000.05
setenv SNPSLMD_LICENSE_FILE $SYNOPSYS/admin/license/key
set path = ($path $SYNOPSYS/$ARCH/syn/bin )
unix% cd bc_tutorial/synthesis
For purposes of this lab and the others, some preliminary setup is done for you. Enter
unix% ls -a.
Notice the files .synopsys_dc.setup and
.synopsys_aliases.
The .synopsys_aliases file contains the
following:
alias rdl "report_design_lib work"
This provides a substitute to execute the Behavioral Compiler
report_design_lib work function.
The .synopsys_dc.setup file is a startup file for both Design Compiler and Behavioral Compiler. This startup file is specific for this lab. You can also have user level startups and enterprise-wide startups.
The file .synopsys_dc.setup contains the following commands and variables that are applicable for both Verilog and VHDL:
target_library = tc6a_cbacore.db;
link_library = { "*", tc6a_cbacore.db};
symbol_library = tc6a_cbacore.sdb;
synthetic_library = {"dw01.sldb" "dw02.sldb" "dw03.sldb"}
vhdlout_bit_type = std_logic;
vhdlout_bit_vector_type = std_logic_vector;
vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "IEEE.std_logic_unsigned.all"}
define_design_lib work -path ./Des_Lib
search_path = search_path + ./VHDL + ./Verilog + ./DB + ./Scripts
bc_enable_analysis_info = true /* BCView */
bc_estimate_timing_effort = zero /* No extra Timing Estimations */
hdlin_store_assignment_delay = false /* Set to true if you have transport delay */
These commands and variables set up Behavioral Compiler in an automated, custom way so you do not have to enter of these commands each time you start Behavioral Compiler. Because each design can have its own .synopsys_dc.setup file, you are defining the operating conditions that are custom for a design and independent from other designs.
unix% bc_shell
If the Behavioral Compiler shell invokes correctly, you may continue. If it does not invoke correctly, check your environmental variable settings or check with your system administrator.
Notice the prompt has changed from unix% to bc_shell> indicating you can now enter Design Compiler or Behavioral Compiler commands.
List the variables used within Behavioral Compiler. These are a combination of the defaults in the tool and those that have been set with the .synopsys_dc.setup file. The list of variables is extremely long. This shows you how many items are under your control in Behavioral Compiler.
bc_shell% list -variables bc
You can also enter the list command with no arguments to obtain a list of the other things list can show you about Behavioral Compiler.
bc_shell% list
At this point you are ready to begin working with Behavioral Compiler. Exit the tool and go on to the next tutorial section.
bc_shell% exit
On to Chapter 2 - Synthesis for Verilog or