Chapter4 - Simulation
Contents
Introduction
Doing the Lab
The objective of behavioral design is to have a single design
that will simulate and synthesize the same way at the behavioral
level, at the RTL level, and finally at the gate level.
This chapter introduces considerations to allow you to make this
happen.
Note: This section assumes the user has the VCS simulator. If you
are using another simulator, that is fine, but, in the interest of
simplicity, no attempt is made here to cover other simulators.
Ideally, the design at the behavior level, the RTL level, and the
gate level all simulate the same using the same test bench.
If you are using cycle-fixed mode for your I/O, generally the
testbench will simulate the same for the three levels.
On the other hand, if you are using superstate-fixed mode
you may have to include code in your design to handle handshaking
signals. Because superstate-fixed mode inserts clock cycles
as needed for synthesis, the RTL (and consequently the gate)
level can differ from the original behavioral level design.

In this tutorial we will not get into the topic of writing
testbenches. Writing testbenches and dealing with handshake
is addressed in the
Behavioral Compiler class.
In this lab we will use a testbench
tb_complex_mult.v to first simulate the behavior code,
then to simulate the scheduled design at the RTL level.
Behavioral Level Simulation
Set your working directory to simulation
unix% cd simulation
Set your working directory to the language of your choice
(Verilog or VHDL)
unix% cd Verilog
or
unix% cd VHDL
The vcs simulator does not use the .synopsys_dc.setup file so
the path setup we used in the previous tutorial sections to
choose between Verilog and VHDL no longer apply.
Invoke the simulator in graphic (-RI) mode. Use the first
command if you are working in the Verilog directory or use the
second if you are working in the VHDL directory:
unix% vcs -RI -line -cc gcc tb_complex_mult.v comp_mult.v
unix% vcs -RI -line -cc gcc tb_complex_mult.vhd comp_mult.vhd
Two windows display, the VirSim window and the VirSim for
Synopsys - Interactive - SIM window, which we will refer to
as the Interactive window for the remainder of this lab.
Move the VirSim window up near the top left of your display.
In the VirSim window, select Hierarchy, then select Waveform
In the Hierarchy window,
- Click the Left mouse button once on tb_complex_mult, you will
see signal names in the bottom right window
- Select the first signal (clk) with the left mouse, scroll down the
signal list to the bottom, and shift-click the left mouse on the last
signal (reset). All signals are highlighted.
- Use the middle mouse button to drag the selected signals into
the waveform window.

- In the control window, click the Run button

Look at the waveforms in the Waveform window. Use the zoom
buttons and waveform scroll bar to adjust the display.
Answer the following questions:
- Does the design wait for the testbench to send it valid data? _______
- Is the two-way handshake working the way you would expect?
(You will likely have to look at the testbench and design source code
to determine this)
- How many cycles does it take from the time the design is
ready for data until the time it has the output ready? ________________
Exit the simulator by clicking the Exit button in the VirSim
window.
Click No in the dialog box asking if we want to save our results.
We are now done with the behavioral level simulation.
RTL Level Simulation
If this lab step fails with a file not found error or similar, stay in
the current directory and re-run the steps you performed in Chapter2
to create the proper comp_mult_sched.v or comp_mult_sched.vhd file.
If you are working in the Verilog directory, execute the following:
unix% vcs -RI -line -cc gcc tb_complex_mult.v comp_mult_sched.v
If you are working in the VHDL directory, execute the following:
unix% vcs -RI -line -cc gcc tb_complex_mult.vhd comp_mult_sched.vhd
As before, use the simulator windows to analyze the behavior of your
design.
- Does the design wait for the testbench to send it valid data? _______
- Is the two-way handshake working the way you would expect?
(You will likely have to look at the testbench and scheduled design code
to determine this)
- How many cycles does it take from the time the design is
ready for data until the time it has the output ready? ________________
Comparison of these two simulation runs shows you that a common
testbench may be used at all levels of synthesis.
If you find differences, you need to determine if the differences
are resolvable by changing the original source code or if you can
simply change constraints to achieve your goal.

As the above illustration shows, the paths available to create
a design that simulates the same at all three levels includes
changes at the behavioral level and/or changes of constraints.
On to Chapter 5 - Some Final Thoughts