Behavioral Compiler Tutorial

Revision 2001.01
Use the Netscape browser to open and view this tutorial.

This tutorial is an introduction to the Synopsys Behavioral Compiler. It shows you the advantages of technology-independent and architecture-independent behavioral designing methodology and

The estimated completion time for the tutorial is 1 to 3 hours. After completing this introduction to Behavioral Compiler, you can take the Synopsys 3 or 4 day class to learn about behavioral synthesis in greater depth.

Two excellent reference books on behavioral synthesis are the following:

Optimal Use of the Tutorial

For optimal use of the tutorial, display the tutorial and run Behavioral Compiler on the same UNIX workstation. This gives you the advantage of copying and pasting examples and commands from the tutorial into the Behavioral Compiler command line interface (bc_shell).

Downloading the Tutorials

Copy the tutorial files into your workstation. Assuming you copied the tutorial files in your home directory, the structure is similar to the following:

Accessing the Tutorials

After you copy the tutorial files into your workstation, use the Netscape File > Open Page command to browse for the bc_tutorial/tutorial/tutorial.html file, or enter the following in the Location field:


where ///+path_to_your+ is 2 forward slash characters followed by the absolute path (including its leading slash character for a total of 3 slashes) to the location of your bc_tutorial directory. For example:


Accessing the Lab Material

To access the lab material, change to the synthesis, coding, or simulation directory in the bc_tutorial directory, for example

cd /bc_tutorial/synthesis

Each lab directory contains a Verilog version and a VHDL version of the lab so you can work with either HDL language.

Execute the labs in the following order:

Starting the Tutorial

Click on the link below to go to Chapter 1 or any of the other chapters in this tutorial

Chapter1 - Getting Started

Chapter2 - Synthesis with Verilog

Chapter2v - Synthesis with VHDL

Chapter3 - Coding for Synthesis with Verilog

Chapter3v - Coding for Synthesis with VHDL

Chapter4 - Simulation

Chapter5 - Some Final Thoughts